1. Field of the Invention
The present invention relates to a cursor memory which stores data representing a cursor pattern (referred to as "pattern data" hereinafter).
2. Description of the Background Art
First of all, a cursor pattern is a pattern that is displayed on a monitor and moves thereon in accordance with mouse operation and the like. A typical example of the cursor pattern is shown in FIG. 7. The cursor pattern CUR.sub.-- P of FIG. 7 is constituted by 64.times.64 pixels. Discussion will be presented below, using the cursor pattern CUR.sub.-- P.
A structure of pattern data CUR.sub.-- D which represent the cursor pattern CUR.sub.-- P will be discussed. FIG. 8 is a schematic view showing the structure of the pattern data CUR.sub.-- D. Each pixel of the cursor pattern CUR.sub.-- P is expressed by using two bits (a shallow bit and a deep bit). Pattern data CUR.sub.-- D0 is a set of shallow bits, which is constituted by 64.times.64 bits in total (64 bits in a vertical direction and 64 bits in a horizontal direction). Pattern data CUR.sub.-- D1 is a set of deep bits, which is constituted by 64.times.64 bits in total (64 bits in a vertical direction and 64 bits in a horizontal direction). For example, a pixel P00 of FIG. 7 is expressed by a shallow bit P00.sub.-- 0 in the pattern data CUR.sub.-- D0 of FIG. 8 and a deep bit P00.sub.-- 1 in the pattern data CUR.sub.-- D1.
Each pixel of the cursor pattern CUR.sub.-- P, which employs two bits, can express four kinds of colors. For example, it expresses transparent, red, black and green when the combination of the shallow bit and the deep bit is 0:0, 0:1, 1:0 and 1:1, respectively.
A cursor memory is a dual port memory for storing the pattern data CUR.sub.-- D. A dual port memory has two ports, each of which performs either or both of input and output of data.
FIG. 9 is a block diagram showing a configuration of a background-art cursor memory 200 used for the cursor pattern CUR.sub.-- P.
The configuration of the cursor memory 200 will be discussed. The cursor memory 200 comprises a cursor memory body 201 for storing the pattern data CUR.sub.-- D, a read circuit 202 for performing read of the pattern data CUR.sub.-- D0 and the pattern data CUR.sub.-- D1 from the cursor memory body 201 and a read/write circuit 203 for performing read and write of the pattern data CUR.sub.-- D0 and the pattern data CUR.sub.-- D1 from and to the cursor memory body 201.
The cursor memory body 201 has the following configuration as the pattern data CUR.sub.-- D are inputted or outputted in units of 32 bits through a read/write port P1. The cursor memory body 201 includes planes P.sub.-- 0 and P.sub.-- 1 for storing the pattern data CUR.sub.-- D0 and the pattern data CUR.sub.-- D1, respectively. Each of the planes P.sub.-- 0 and P.sub.-- 1 is a memory cell array of 64 rows and 64 columns. In each row of the memory cell array, an address is allocated every 32 columns. Specifically, addresses #0 to #127 are allocated in the plane P.sub.-- 0 and addresses #128 to #255 are allocated in the plane P.sub.-- 1. At each address, 32 bits of data are stored.
The read/write circuit 203 comprises the read/write port P1 used for input and output of the pattern data CUR.sub.-- D0 and CUR.sub.-- D1. The read/write port P1 includes 32 terminals and performs input and output of the pattern data CUR.sub.-- D in units of 32 bits through the 32 terminals.
The read circuit 202 comprises a multiplexer MUX, shift registers SR0 and SR1, a read port P2 and a control circuit CTL2.
The read port P2 performs only output of the pattern data CUR.sub.-- D and includes two terminals for clear discrimination between the pattern data CUR.sub.-- D0 and the pattern data CUR.sub.-- D1.
The read circuit 202 outputs the pattern data CUR.sub.-- D0 and CUR.sub.-- D1 to the two terminals of the read port P2 respectively by bit. Accordingly, the cursor memory body 201 may fundamentally have a configuration to output the pattern data CUR.sub.-- D0 and the pattern data CUR.sub.-- D1 by bit. For effective use of circuit area, however, the cursor memory body 201 has a configuration to output data to the read circuit 202 in units of 32 bits (one address of data) in accordance with the 32-bit output to the read/write circuit 203.
The multiplexer MUX receives the 32 bits of data read by the cursor memory body 201. The multiplexer MUX outputs the received 32 bits of data to the shift register SR0 when the 32 bits of data are the pattern data CUR.sub.-- D0 and to the shift register SRI when the 32 bits of data are the pattern data CUR.sub.-- D1. The shift registers SR0 and SR1 output the pattern data CUR.sub.-- D0 and CUR.sub.-- D1, respectively, to the read port P2 by bit in accordance with a clock (not shown) supplied from the outside of the cursor memory 200.
The input/output operation through the read/write port P1 is performed on one of the pattern data CUR.sub.-- D0 and CUR.sub.-- D1. In contrast, the output operation through the read port P2 has to be performed simultaneously on both the pattern data CUR.sub.-- D0 and CUR.sub.-- D1. That's because the color of each pixel is not determined unless both the shallow bit and the deep bit of each pixel of the cursor pattern CUR.sub.-- P become available. The reading of the pattern data CUR.sub.-- D from the cursor memory body 201 to the read port P2 is performed in units of 32 bits in accordance with the reading of the pattern data CUR.sub.-- D from the cursor memory body 201 to the read/write port P1, for effective use of circuit area.
The read/write port P1 and the read port P2 perform the input/output of the pattern data CUR.sub.-- D asynchronously and concurrently.
The background-art cursor memory 200 with the above-discussed configuration has the following problem: The control circuit CTL2 controls the cursor memory body 201 and the read circuit 202 through the following steps as shown in FIG. 10 to display one line of cursor pattern CUR.sub.-- P of FIG. 7:
(A0) Variables i, j and k are initialized (Step S201).
(A1) The control circuit CTL2 sets a column address PY to 0. The cursor memory body 201 reads the 32-bit data stored at the address #0. The read circuit 202 stores the read data into the shift register SR0 (Steps S202 to S204 and S208 to S211).
(A2) The control circuit CTL2 sets to the column address PY to 2. The cursor memory body 201 reads the 32-bit data stored at the address #128. The read circuit 202 stores the read data into the shift register SR1 (Steps S202, S203, S205, S208 to S210, S212 and S213).
(A3) The shift registers SR0 and SR1 output one bit out of the stored 32-bit data in accordance with the clock (Step S214).
(A4) Repeating the operation of Step S214 thirty-one times, the shift registers SR0 and SR1 output all of the stored 32-bit data (Steps S214 to S217).
(A5) The control circuit CTL2 sets the column address PY to 1. The cursor memory body 201 reads the 32-bit data stored at the address #1. The read circuit 202 stores the read data into the shift register SR0 (Steps S202, S203, S206 and S208 to S211).
(A6) The control circuit CTL2 sets the column address PY to 3. The cursor memory body 201 reads the 32-bit data stored at the address #129. The read circuit 202 stores the read data into the shift register SR1 (Steps S202, S203, S207 to S210, S212 and S213).
(A7) The shift registers SR0 and SR1 output one bit out of the stored 32-bit data in accordance with the clock (Step S214).
(A8) Repeating the operation of Step S214 thirty-one times, the shift registers SR0 and SR1 output all of the stored 32-bit data (Steps S214 to S217).
Such a complicated control as described above is disadvantageously required as it is necessary to set to the column address PY to 0,1,2 and 3 in this order. Therefore, the configuration of the control circuit CTL2 becomes more complicated. As to the cursor memory 200 on the whole, its operating speed is limited and its circuit scale is enlarged. Moreover, if the operating speed of the cursor memory can not meet the actually-required one, another circuit is further needed to accommodate the speed differential. cl SUMMARY OF THE INVENTION
The present invention is directed to a cursor memory from and to which first pattern data and second pattern data constituting cursor pattern data are read and written. According to a first aspect of the present invention, the cursor memory comprises: a cursor memory body for storing the first and second pattern data; reading means for performing reading of the first and second pattern data from the cursor memory body; and read/write means for performing read and write of the first and second pattern data from and to the cursor memory body. In the cursor memory of the first aspect, the cursor memory body comprises a first bank including a first block for storing low-order bits of the first pattern data and a second block for storing high-order bits of the second pattern data; and a second bank including a third block for storing low-order bits of the second pattern data and a fourth block for storing high-order bits of the first pattern data.
According to a second aspect of the present invention, in the cursor memory of the first aspect, the read/write means comprises a read/write port used for input/output of the first or second pattern data; and a crossbar switch disposed between the read/write port and the cursor memory body, for switching between the high-order bits and the low-order bits depending on whether the first pattern data or the second pattern data should be inputted/outputted through the read/write port.
According to a third aspect of the present invention, in the cursor memory of the second aspect, the crossbar switch is controlled by a read/write address signal for designating an address in the cursor memory body when the read/write means performs the read and write.
According to a fourth aspect of the present invention, in the cursor memory of the first aspect, the read means comprises a read port used for output of the first and second pattern data; and a crossbar switch disposed between the read port and the cursor memory body, for switching between the first pattern data and the second pattern data depending on whether the high-order bits or the low-order bits should be outputted through the read port.
According to a fifth aspect of the present invention, in the cursor memory of the fourth aspect, the crossbar switch is controlled by a read address signal for designating an address in the cursor memory body when the read means performs the read.
According to a sixth aspect of the present invention, in the cursor memory of the fourth aspect, the read means further comprises shift registers disposed between the crossbar switch and the read port, for outputting the first and second pattern data to the read port by bit.
According to a seventh aspect of the present invention, in the cursor memory of the first aspect, the first to fourth blocks are arranged so as to be sequentially designated by an address signal for designating an address in the cursor memory body.
According to an eighth aspect of the present invention, in the cursor memory of the seventh aspect, the read means comprises an incrementer for generating the address signal.
According to a ninth aspect of the present invention, in the cursor memory of the sixth aspect, the read means further comprises a shift-register control counter for controlling the shift register.
According to a tenth aspect of the present invention, in the cursor memory of the ninth aspect, the first to fourth blocks are arranged so as to be sequentially designated by an address signal for designating an address in the cursor memory body, the read means comprises an incrementer for generating the address signal; and a block counter for counting the number of the blocks in the first or second bank, and the shift-register control counter and the incrementer are controlled by the block counter.
According to an eleventh aspect of the present invention, in the cursor memory of the tenth aspect, the read means receives a load signal inputted to the inside of the cursor memory from the outside for requesting the read means to start the read, and the shift-register control counter, the incrementer and the block counter start their respective operations based on the load signal.
According to a twelfth aspect of the present invention, in the cursor memory of the first aspect, the cursor memory body receives a read/write address signal for designating an address in the cursor memory body when the read/write means performs the read and write; and a read address signal for designating an address in the cursor memory body when the read means performs the read, and the read/write address signal and the read address signal are common.
In the cursor memory of the first aspect, with the first and second banks, the read means can make a control to simultaneously read the first and second pattern data. That simplifies the control by the control means, to thereby achieve an efficient use of the circuit area.
In the cursor memory of the second aspect, the operation of the read/write means can be implemented by simply-configured crossbar switch.
The cursor memory of the third aspect achieves the control over the crossbar switch by using the read/write address signal.
In the cursor memory of the fourth aspect, the operation of the read means can be implemented by simply-configured crossbar switch.
The cursor memory of the fifth aspect achieves the control over the crossbar switch by using the read address signal.
The cursor memory of the sixth aspect has only to provide the shift registers between the crossbar switch and the read port since the read means can receive data from the cursor memory body which allows simultaneous reading of the first and second pattern data, instead of sequential read.
The cursor memory of the seventh aspect simplifies the design of the cursor memory.
In the cursor memory of the eighth aspect, the block can be designated by using the simply-configured incrementer since the blocks in each bank are arranged so as to be sequentially designated.
In the cursor memory of the ninth aspect, the shift-register control counter has only to control the shift operation by the number of high-order bits or low-order bits and therefore reduction in circuit area of the counter is achieved.
The cursor memory of the tenth aspect can perform the reading of the cursor pattern data by controlling the shift registers and the incrementer with the block counter.
The cursor memory of the eleventh aspect can start the reading of the cursor pattern data by simply supplying the load signal.
The cursor memory of the twelfth aspect simplifies the design of the cursor memory.
An object of the present invention is to provide an easy-controllable cursor memory.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.